The goals for the entire integrated circuit (IC) packaging industry include faster, more reliable, and higher-density circuits, produced at lower cost to produce smaller devices for cellphones, video cameras, portable music players, etc. The goals of packaging IC for the future will be met by reducing the number of internal interconnections and increasing the density of chips.
Various techniques, such as, flip chip, ball grid array (BGA), chip on board (COB), and multi-chip modules (MCM), have been developed to meet the continued demands for improving system performance and hardware capabilities, while the space in which to provide these improved hardware capabilities continues to decrease.
Multiple integrated circuit devices may be fabricated within a single package, thereby forming a MCM. A single MCM may include two or more discrete integrated circuit devices, which may be arranged one on top of one another over a substrate (i.e.—vertically stacked). This mounting technique permits a higher density of chips or integrated circuits on the MCM substrate. The substrate may include one or more layers of electrically conductive material separated by dielectric materials.
Although vertically stacked MCM's may increase the effective density of chips, over that of horizontally placed MCM components, it has the disadvantage in that the MCM's must usually be assembled before the component chips and chip connections can be tested. These extra manufacturing steps can lead to increased cost and decreased product yield if the chips are defective.
Another common problem associated with vertically stacked MCM's is that the bottom chip must be larger than the top chip to accommodate the plurality of bond pads located on the bottom chip. Due to the constraint of limited space available for mounting individual chips on a substrate, the larger configuration of the bottom chip decreases the number of chips per semiconductor wafer, and correspondingly, increases the cost of manufacturing.
Another manufacturing technique is vertically stacked packaging (i.e., a package on package configuration). However, this manufacturing process has its own problems, such as, local and global planarization inconsistencies.
Additionally, the mold cap of a bottom package in a package on package structure must be kept thin; otherwise, the ball diameters of the solder balls formed on the top substrate must be excessively large in order to contact the bottom package. However, thin mold caps can cause their own problems during package on package assembly, such as, restricted selection of epoxy mold compounds.
In other packaging, the top package normally has at least the package size to clear the bottom mold cap dimensions with large solder balls arranged in the peripheral area. This results in an unnecessarily large package size to match the bottom package footprint.
Furthermore, package structures are prone to mechanical damage during test handling which further slows the testing process and system throughput.
Thus, despite recent developments in semiconductor packaging techniques, a need still remains for improved packaging device structures and methods of fabrication for increasing semiconductor chip densities while protecting package structures during test handling. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.